1. Technical Field
The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor memory device having a vertical gate cell and a method of manufacturing the same.
2. Related Art
Semiconductor memory devices may have features of low power consumption in addition to a non-volatile property of a flash memory device, a high-speed operation of a static random access memory (SRAM), and a high integration of a dynamic random access (DRAM). Devices such as ferroelectric random access memories (FRAMs), magnetic random access memories (MRAMs), phase-change random access memories (PCRAMs), or nano floating gate memories (NFGM) may provide the above listed features.
For example, a diode has been used as a switching device of the semiconductor memory device. However, when the diode is applied as the switching device, the semiconductor memory device may have the following features.
FIG. 1 is a circuit diagram of a semiconductor memory device including a switching device according to the conventional art.
Referring to FIG. 1, the semiconductor memory device has a multi-level stack (MLS) structure including a lower-level cell A and an upper-level cell B. The lower-level cell A and the upper-level cell B are formed below and above a common word line 20, respectively. The lower-level cell A includes of a diode 12 serving as a switching device and a phase-change material 16 formed between a first bit line 10 and the common word line 20, and the upper-level cell B includes of a diode 22 serving as a switching device and a phase-change material 26 formed between the common word line 20 and a second bit line 30.
FIG. 2 illustrates cross-sectional structure corresponding to the semiconductor memory device of FIG. 1
Referring to FIG. 2, a lower-level cell that includes a diode 12, a heater 14, and a phase-change material 16, which are sequentially formed, is formed on a first bit line 10. The lower-level cell further includes a buried insulating layer 18 formed between adjacent lower-level cells.
A common word line 20 is formed on the lower-level cell, and an upper-level cell is formed on the common word line 20. The upper-level cell includes a diode 22, a heater 24, and a phase-change material 26, which are sequentially formed. A buried insulating layer 28 is formed between the adjacent upper-level cells. A second bit line is formed on the upper-level cell.
In the conventional art as shown in FIGS. 1 and 2, the diodes 12 and 22 are formed as a switching device of the semiconductor memory device.
When the diode is used as the switching device, word lines and bit lines, which are individually separated, are needed to select the diodes. However, the word line and bit line are formed to be smaller as semiconductor memory devices are further integrated, and thus, a resistance of the word line is gradually increased. With an increase in the resistance of the word line, a voltage of the word line becomes closer to 0 Volt in a write or read operation of a cell, and thus, a voltage applied to the cell is reduced, which results in reduction in a read/write sensing margin. More specifically, a low resistance state of a cell is sensed as a high resistance state due to the increase in the voltage of the word line so that a word line bouncing to reduce a read sensing margin is caused.
In addition, as critical dimensions (CDs) of the word line and the bit line are reduced according to the further integration of the semiconductor memory device, an interconnection line resistance is gradually increased, and thus, an internal operation voltage is increased.
In addition, when the diode is formed as the switching device, all mask processes are performed with a cell pitch, a fabrication process is complicated, and production cost is increased.